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ERSA
2006
86views Hardware» more  ERSA 2006»
9 years 9 months ago
GifT: A Gravity-Directed and Life-Time Based Algorithm for Temporal Partitioning of Data Flow Graphs
In reconfigurable systems, reconfiguration latency has a significant impact on the system performance. In this work, a temporal partitioning algorithm is presented to partition da...
Farhad Mehdipour, Morteza Saheb Zamani, Mehdi Sedi...
CATA
2007
9 years 9 months ago
Static Scheduling for Synchronous Data Flow Graphs
This paper addresses the issue of determining the iteration bound for a synchronous data flow graph (SDFG) and determining whether or not a SDFG is live based on some calculations...
Samer F. Khasawneh, Michael E. Richter, Timothy W....
ISLPED
1995
ACM
100views Hardware» more  ISLPED 1995»
9 years 11 months ago
Simultaneous scheduling and binding for power minimization during microarchitecture synthesis
ABSTRACT { Sub-micron technologies and the increasing size and complexity of integrated components have aggravated the e ect of long interconnects and buses, compared to that of ga...
Aurobindo Dasgupta, Ramesh Karri
CODES
2004
IEEE
9 years 11 months ago
Hardware synthesis from coarse-grained dataflow specification for fast HW/SW cosynthesis
This paper concerns automatic hardware synthesis from data flow graph (DFG) specification for fast HW/SW cosynthesis. A node in DFG represents a coarse grain block such as FIR and...
Hyunuk Jung, Soonhoi Ha
ISSS
2000
IEEE
144views Hardware» more  ISSS 2000»
10 years 14 days ago
Efficient Hardware Controller Synthesis for Synchronous Dataflow Graph in System Level Design
This paper concerns automatic hardware synthesis from data flow graph (DFG) specification in system level design. In the presented design methodology, each node of a data flow gra...
Hyunuk Jung, Kangnyoung Lee, Soonhoi Ha
GLVLSI
2000
IEEE
104views VLSI» more  GLVLSI 2000»
10 years 15 days ago
A new technique for estimating lower bounds on latency for high level synthesis
In this paper we present a novel and fast estimation technique that produces tight latency lower bounds for Data Flow Graphs representing time critical segments of the application...
Helvio P. Peixoto, Margarida F. Jacome
DATE
2010
IEEE
135views Hardware» more  DATE 2010»
10 years 1 months ago
Mapping scientific applications on a large-scale data-path accelerator implemented by single-flux quantum (SFQ) circuits
— To overcome issues originating from the CMOS technology, a large-scale reconfigurable data-path (LSRDP) processor based on single-flux quantum circuits is introduced. LSRDP is ...
Farhad Mehdipour, Hiroaki Honda, Hiroshi Kataoka, ...
IPPS
2007
IEEE
10 years 2 months ago
C++ based System Synthesis of Real-Time Video Processing Systems targeting FPGA Implementation
Implementing real-time video processing systems put high requirements on computation and memory performance. FPGAs have proven to be effective implementation architecture for thes...
Najeem Lawal, Mattias O'Nils, Benny Thörnberg
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