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ASPDAC
1999
ACM

The Hierarchical h-Adaptive 3-D Boundary Element Computation of VLSI Interconnect Capacitance

9 years 8 months ago
The Hierarchical h-Adaptive 3-D Boundary Element Computation of VLSI Interconnect Capacitance
: In VLSI circuits with deep sub-micron, the parasitic capacitance from interconnect is a very important factor determining circuit performances such as power and time-delay. The Boundary Element Method(BEM) is an effective tool for solving Laplacian’s equation applied in the parasitic capacitance extraction. In this paper, a hierarchical h-adaptive BEM is presented . It constructs a 3-D linear hierarchical shape function based on constant boundary element and uses previous computations and solutions. Hence, it reduces much computation in adaptive procedure. Besides, a combination of residualtype estimator and reduced Z-Z error estimator for more reliable and efficient estimation of error is presented. Some numerical results show that this method is effective. Key words: Parasitic Capacitance, Boundary Element Method, Hierarchical h-Adaptive Computation, VLSI
Jinsong Hou, Zeyi Wang, Xianlong Hong
Added 02 Aug 2010
Updated 02 Aug 2010
Type Conference
Year 1999
Where ASPDAC
Authors Jinsong Hou, Zeyi Wang, Xianlong Hong
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