CMG
2000
13 years 6 months ago
2000
Our study compares CPU performance on RISC and CISC uni and multiprocessors of varying speeds, and shows that the Instruction Set Architecture (ISA) style no longer matters. Our s...
CSE
2008
IEEE
13 years 6 months ago
2008
IEEE
A well-known challenge during processor design is to obtain best possible results for a typical target application domain by combining flexibility and computational performance. A...
CC
2008
Springer
13 years 7 months ago
2008
Springer
This paper describes the design and implementation of a language for specifying the semantics of an instruction set, along with a run-time system to support the static analysis of ...
ASM
2008
ASM
13 years 7 months ago
2008
ASM
A Virtual Machine (VM) is a program running on a conventional microprocessor that emulates the binary instruction set, registers, and memory space of an idealized computing machine...
MICRO
1991
IEEE
13 years 8 months ago
1991
IEEE
This paper examines two alternative approaches to supporting code scheduling for multiple-instruction-issue processors. One is to provide a set of non-trapping instructions so tha...
SWAT
2000
Springer
13 years 8 months ago
2000
Springer
We consider dictionaries over the universe U = {0, 1}w on a unit-cost RAM with word size w and a standard instruction set. We present a linear space deterministic dictionary with m...
APCSAC
2001
IEEE
13 years 8 months ago
2001
IEEE
In this paper, a new architecture called the extendable instruction set computer (EISC) is introduced that addresses the issues of memory size and performance in embedded micropro...
ATS
2004
IEEE
13 years 8 months ago
2004
IEEE
TIS (Test Instruction Set) is an instruction level technique for CPU core self-testing. This method is based on enhancing a CPU instruction set with test instructions. TIS replace...
ICCD
2007
IEEE
13 years 9 months ago
2007
IEEE
As application-specific instruction set processors (ASIPs) are being increasingly used in mobile embedded systems, the ubiquitous networking connections have exposed these systems...
HIPEAC
2007
Springer
13 years 9 months ago
2007
Springer
In this paper, we examine the trade-offs in performance and area due to customizing the datapath and instruction set architecture of a soft VLIW processor implemented in a high-den...