Sciweavers

Share
CMG
2000
8 years 8 months ago
Comparing CPU Performance Between and Within Processor Families
Our study compares CPU performance on RISC and CISC uni and multiprocessors of varying speeds, and shows that the Instruction Set Architecture (ISA) style no longer matters. Our s...
Lee A. Butler, Travis Atkison, Ethan L. Miller
CSE
2008
IEEE
8 years 9 months ago
Application Specific Processors for Multimedia Applications
A well-known challenge during processor design is to obtain best possible results for a typical target application domain by combining flexibility and computational performance. A...
Rashid Muhammad, Ludovic Apvrille, Renaud Pacalet
CC
2008
Springer
111views System Software» more  CC 2008»
8 years 9 months ago
A System for Generating Static Analyzers for Machine Instructions
This paper describes the design and implementation of a language for specifying the semantics of an instruction set, along with a run-time system to support the static analysis of ...
Junghee Lim, Thomas W. Reps
ASM
2008
ASM
8 years 9 months ago
Using EventB to Create a Virtual Machine Instruction Set Architecture
A Virtual Machine (VM) is a program running on a conventional microprocessor that emulates the binary instruction set, registers, and memory space of an idealized computing machine...
Stephen Wright
MICRO
1991
IEEE
85views Hardware» more  MICRO 1991»
8 years 10 months ago
Comparing Static and Dynamic Code Scheduling for Multiple-Instruction-Issue Processors
This paper examines two alternative approaches to supporting code scheduling for multiple-instruction-issue processors. One is to provide a set of non-trapping instructions so tha...
Pohua P. Chang, William Y. Chen, Scott A. Mahlke, ...
SWAT
2000
Springer
107views Algorithms» more  SWAT 2000»
8 years 11 months ago
A New Trade-Off for Deterministic Dictionaries
We consider dictionaries over the universe U = {0, 1}w on a unit-cost RAM with word size w and a standard instruction set. We present a linear space deterministic dictionary with m...
Rasmus Pagh
APCSAC
2001
IEEE
8 years 11 months ago
High-Performance Extendable Instruction Set Computing
In this paper, a new architecture called the extendable instruction set computer (EISC) is introduced that addresses the issues of memory size and performance in embedded micropro...
Heui Lee, Paul Becket, Bill Appelbe
ATS
2004
IEEE
97views Hardware» more  ATS 2004»
8 years 11 months ago
Test Instruction Set (TIS) for High Level Self-Testing of CPU Cores
TIS (Test Instruction Set) is an instruction level technique for CPU core self-testing. This method is based on enhancing a CPU instruction set with test instructions. TIS replace...
Saeed Shamshiri, Hadi Esmaeilzadeh, Zainalabedin N...
ICCD
2007
IEEE
152views Hardware» more  ICCD 2007»
8 years 11 months ago
Compiler-assisted architectural support for program code integrity monitoring in application-specific instruction set processors
As application-specific instruction set processors (ASIPs) are being increasingly used in mobile embedded systems, the ubiquitous networking connections have exposed these systems...
Hai Lin, Xuan Guan, Yunsi Fei, Zhijie Jerry Shi
HIPEAC
2007
Springer
8 years 11 months ago
Customizing the Datapath and ISA of Soft VLIW Processors
In this paper, we examine the trade-offs in performance and area due to customizing the datapath and instruction set architecture of a soft VLIW processor implemented in a high-den...
Mazen A. R. Saghir, Mohamad El-Majzoub, Patrick Ak...
books