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2007
IEEE

Implications of Device Timing Variability on Full Chip Timing

10 years 11 months ago
Implications of Device Timing Variability on Full Chip Timing
As process technologies continue to scale, the magnitude of within-die device parameter variations is expected to increase and may lead to significant timing variability. This paper presents a quantitative evaluation of how low level device timing variations impact the timing at the functional block level. We evaluate two types of timing variations: random and systematic variations. The study introduces random and systematic timing variations to several functional blocks in Intel? CoreTM Duo microprocessor design database and measures the resulting timing margins. The primary conclusion of this research is that as a result of combining two probability distributions (the distribution of the random variation and the distribution of path timing margins) functional block timing margins degrade non-linearly with increasing variability.
Murali Annavaram, Ed Grochowski, Paul Reed
Added 01 Dec 2009
Updated 01 Dec 2009
Type Conference
Year 2007
Where HPCA
Authors Murali Annavaram, Ed Grochowski, Paul Reed
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