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2009
IEEE

Unified Challenges in Nano-CMOS High-Level Synthesis

10 years 7 months ago
Unified Challenges in Nano-CMOS High-Level Synthesis
: The challenges in nano-CMOS circuit design include the following: variability, leakage, power, thermals, reliability, and yield. This talk will focus on interdependent consideration of these challenges during high-level (aka architectural or behavioral) synthesis. The majority of the existing design techniques related to these challenges are at the device or logic level of circuit ion and few are at the architectural level, however, the research is full swing in this direction. At the architecture level, there are balanced degrees of freedom to vary design parameters and take fast and correct design decisions at an early phase of the design cycle without propagating the design errors to lower f circuit abstraction, where it is costly to correct them. In addition, g at higher levels of abstraction is an efficient way to cope with complexity, facilitate design verification, and increase design reuse. For maximizing yield of circuit design in the presence of variability the designers ca...
Saraju P. Mohanty
Added 23 Nov 2009
Updated 23 Nov 2009
Type Conference
Year 2009
Where VLSID
Authors Saraju P. Mohanty
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