Improving the Security of Dual-Rail Circuits

Dual-rail encoding, return-to-spacer protocol and hazard-free logic can be used to resist differential power analysis attacks by making the power consumption independent of processed data. Standard dual-rail logic uses a protocol with a single spacer, e.g. all-zeroes, which gives rise to power balancing problems. We address these problems by incorporating two spacers; the spacers alternate between adjacent clock cycles. This guarantees that all gates switch in each clock cycle regardless of the transmitted data values. To generate these dual-rail circuits an automated tool has been developed. It is capable of converting synchronous netlists into dual-rail circuits and it is interfaced to industry CAD tools. Dual-rail and single-rail benchmarks based upon the Advanced Encryption Standard (AES) have been simulated and compared in order to evaluate the method.

• Type: Conference
• Year: 2004
• Where: CHES
• Authors: Danil Sokolov, Julian Murphy, Alexandre V. Bystrov, Alexandre Yakovlev
• Keywords: CHES 2004, Clock Cycle, Cryptography, Dual-rail Circuits, Standard Dual-rail Logic