Increasing Robustness of SAT-based Delay Test Generation Using Efficient Dynamic Learning Techniques

Due to the increased speed in modern designs, testing for delay faults has become an important issue in the postproduction test of manufactured chips. A high fault coverage is needed to guarantee the correct temporal behavior. Today's ATPG algorithms have difficulties to reach the desired fault coverage due to the high complexity of modern designs. In this paper, we describe how to efficiently integrate the reuse of learned information into state-of-the-art SATbased ATPG algorithms and, by this, reduce the number of unclassified faults significantly. For further reduction, a post-classification phase is presented. Experimental results for ATPG for delay faults on large industrial circuits show the robustness and feasibility of the approach.

• Type: Journal
• Year: 2009
• Where: ETS
• Authors: Stephan Eggersglüß, Rolf Drechsler
• Keywords: Delay Faults, ETS 2009, Fault Coverage, Hardware, Modern Designs