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2007
IEEE

An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy

10 years 10 months ago
An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy
An efficient on-chip infrastructure for memory test and repair is crucial to enhance yield and availability of SoCs. Therefore embedded memories are commonly equipped with spare rows and columns (2D redundancy). To avoid the storage of large failure bitmaps needed by classical algorithms for offline repair analysis, existing heuristics for built-in repair analysis (BIRA) either follow very simple search strategies or restrict the search to smaller local bitmaps. Exact BIRA algorithms work with sub analyzers for each possible repair combination. While a parallel implementation suffers from a high hardware overhead, a serial implementation leads to high test times. The integrated built-in test and repair approach proposed in this paper interleaves test and repair analysis and supports an exact solution without failure bitmap. The basic search procedure is combined with an efficient technique to continuously reduce the problem complexity and keep the test and analysis time low.
Philipp Öhler, Sybille Hellebrand, Hans-Joach
Added 02 Jun 2010
Updated 02 Jun 2010
Type Conference
Year 2007
Where ETS
Authors Philipp Öhler, Sybille Hellebrand, Hans-Joachim Wunderlich
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