Sciweavers

Share
CODES
2008
IEEE

Intra- and inter-processor hybrid performance modeling for MPSoC architectures

9 years 8 months ago
Intra- and inter-processor hybrid performance modeling for MPSoC architectures
The heterogeneity of modern MPSoC architectures, coupled with the increasing complexity of the applications mapped onto them has recently led to a lot of interest in hybrid performance modeling techniques. Here, the idea is to apply different modeling and analysis techniques to different subsystems/components of an architecture/application. Such hybrid techniques often turn out to be more efficient and accurate compared to relying on a single analysis technique for the entire system. However, the challenge associated with this approach is to combine the different analysis results effectively to obtain conservative performance estimates for the entire system. In this paper we study a hybrid scheme where certain system components are simulated (e.g. using instruction set simulators), whereas others are analyzed using a formal technique called Real-Time Calculus (RTC). The main novelty of our approach stems from our use of this hybrid technique even for multiple tasks mapped onto a sing...
Frank E. B. Ophelders, Samarjit Chakraborty, Henk
Added 29 May 2010
Updated 29 May 2010
Type Conference
Year 2008
Where CODES
Authors Frank E. B. Ophelders, Samarjit Chakraborty, Henk Corporaal
Comments (0)
books