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3DIC
2009
IEEE

Junction-level thermal extraction and simulation of 3DICs

10 years 10 days ago
Junction-level thermal extraction and simulation of 3DICs
Abstract—In 3DICs heat dissipating devices are stacked directly on top of each other leading to a higher heat density than in a comparable 2D chip. 3D integration also moves the majority of active devices further away from the heatsink. This results in a degraded thermal path which makes it more challenging to remove heat from the active devices. Gradient FireBolt was used to perform an appropriate 3D thermal analysis on a 1024-point, memory-on-logic 3DIC FFT processor for synthetic aperture radar (SAR). The chip was simulated with a spatial resolution of 80 nm, and was modeled to include the effect of each line of interconnect, as well as each via and fill structure exactly as drawn in the layout. Large isolated temperature spikes were found near groups of clock buffers at the edge of the SRAMs on the middle tier. It was found that lowering the simulation resolution and using composite thermal conductivities failed to accurately predict the location of these tentpoles.
Samson Melamed, Thorlindur Thorolfsson, Adi Sriniv
Added 18 May 2010
Updated 18 May 2010
Type Conference
Year 2009
Where 3DIC
Authors Samson Melamed, Thorlindur Thorolfsson, Adi Srinivasan, Edmund Cheng, Paul D. Franzon, Rhett Davis
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