Latency-Guided On-Chip Bus Network Design

10 years 7 months ago
Latency-Guided On-Chip Bus Network Design
Abstract— Deep submicron technology scaling has two major ramifications on the design process. First, reduced feature size significantly increases wire delay, thus resulting in critical paths being dominated by global interconnect rather than gate delays. Second, ultra-high level of integration mandates design of systems-on-chip that encompass numerous design blocks of decreased functional granularity and increased communication demands. The convergence of these two factors emphasizes the importance of the on-chip bus network as one of the crucial high-performance enablers for future systems-on-chip. We have developed an on-chip bus network design methodology and corresponding set of tools which, for the first time, close the synthesis loop between system and physical design. The approach has three components: a communication profiler, a bus network designer, and a fast approximate floorplanner. The communication profiler collects run-time information about the traffic between...
Milenko Drinic, Darko Kirovski, Seapahn Meguerdich
Added 31 Jul 2010
Updated 31 Jul 2010
Type Conference
Year 2000
Authors Milenko Drinic, Darko Kirovski, Seapahn Meguerdichian, Miodrag Potkonjak
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