Library cell layout with Alt-PSM compliance and composability

The sustained miniaturization of VLSI feature size presents great challenges to sub-wavelength photolithography and requests usage of many Resolution Enhancement Techniques (RET). The difficulty and feasibility of deploying the RET such as Alternating Phase Shifting Mask (Alt-PSM) depend heavily on circuit layout. In this paper, we propose a Boolean satisfiability (SAT) based library cell layout method that can achieve AltPSM compliance and composability in a constructive manner. Compared to previously reported post processing approach, our method often leads to further cell area efficiency improvement.

• Type: Conference
• Year: 2005
• Where: ASPDAC
• Authors: Ke Cao, Puneet Dhawan, Jiang Hu
• Keywords: ASPDAC 2005, Cell Layout Method, Phase Shifting Mask, VLSI Feature Size