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DATE
2004
IEEE

A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation

13 years 7 months ago
A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation
This paper describes a novel design methodology to implement a secure DPA resistant crypto processor. The methodology is suitable for integration in a common automated standard cell ASIC or FPGA design flow. The technique combines standard building blocks to make `new' compound standard cells, which have a close to constant power consumption. Experimental results indicate a 50 times reduction in the power consumption fluctuations.
Kris Tiri, Ingrid Verbauwhede
Added 20 Aug 2010
Updated 20 Aug 2010
Type Conference
Year 2004
Where DATE
Authors Kris Tiri, Ingrid Verbauwhede
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