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    DATE
    2004
    IEEE
    149views Hardware» more  DATE 2004»
    A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation
    13 years 8 months ago
    A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation
    Download  www.ee.ucla.edu
    This paper describes a novel design methodology to implement a secure DPA resistant crypto processor. The methodology is suitable for integration in a common automated standard ce...
    Kris Tiri, Ingrid Verbauwhede
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