Logical Verification of the NVAX CPU Chip Design

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Logical Verification of the NVAX CPU Chip Design
ct Digital's NVAX high-performance microprocessor has a complex logical design. A rigorous simulation-based verification effort was undertaken to ensure that there were no logical errors. At the core of the effort were implementation-oriented, directed, pseudorandom exercisers. These exercisers were supplemented with implementation-specific focused tests and existing VAX architectural tests. Only 15 logical bugs, all unobtrusive, were detected in the first-pass design, and the operating system booted with first-pass chips in a prototype system.
Walker Anderson
Added 10 Aug 2010
Updated 10 Aug 2010
Type Conference
Year 1992
Where ICCD
Authors Walker Anderson
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