A Low-Overhead Asynchronous Interconnection Network for GALS Chip Multiprocessors

A new asynchronous interconnection network is introduced for globally-asynchronous locally-synchronous (GALS) chip multiprocessors. The network eliminates the need for global clock distribution, and can interface multiple synchronous timing domains operating at unrelated clock rates. In particular, two new highly-concurrent asynchronous components are introduced which provide simple routing and arbitration/merge functions. Post-layout simulations in identical commercial 90nm technology indicate that comparable recent synchronous router nodes have 5.6-10.7x more energy per packet and 2.86.4x greater area than the new asynchronous nodes. Under random traffic, the network provides significantly lower latency and competitive throughput over the entire operating range of the 800 MHz network and through mid-range traffic rates for

• Type: Journal
• Year: 2010
• Where: NOCS
• Authors: Michael N. Horak, Steven M. Nowick, Matthew Carlberg, Uzi Vishkin
• Keywords: Asynchronous Interconnection Network, Computer Networks, Multiple Synchronous Timing, NOCS 2010, Synchronous Router Nodes