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2011

Low-Power Clock Tree Design for Pre-Bond Testing of 3-D Stacked ICs

8 years 1 months ago
Low-Power Clock Tree Design for Pre-Bond Testing of 3-D Stacked ICs
—Pre-bond testing of 3-D stacked integrated circuits (ICs) involves testing each individual die before bonding. The overall yield of 3-D ICs improves with pre-bond testability because manufacturers can avoid stacking defective dies with good ones. However, pre-bond testability presents unique challenges to 3-D clock tree design. First, each die needs a complete 2-D clock tree to enable pre-bond test. Second, the entire 3-D stack needs a complete 3-D clock tree for post-bond test and operation. In the case of a two-die stack, a straightforward solution is to have two complete 2-D clock trees connected with a single through-silicon-via (TSV). We show that this solution suffers from long wirelength (WL) and high clock power consumption. Our algorithm improves on this solution, minimizes the overall WL and clock power consumption, and provides both prebond testability and post-bond operability with minimum skew and constrained slew. Compared with the single-TSV solution, SPICE simulation...
Xin Zhao, Dean L. Lewis, Hsien-Hsin S. Lee, Sung K
Added 15 May 2011
Updated 15 May 2011
Type Journal
Year 2011
Where TCAD
Authors Xin Zhao, Dean L. Lewis, Hsien-Hsin S. Lee, Sung Kyu Lim
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