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ICCAD
2009
IEEE

Pre-bond testable low-power clock tree design for 3D stacked ICs

9 years 1 months ago
Pre-bond testable low-power clock tree design for 3D stacked ICs
Pre-bond testing of 3D stacked ICs involves testing individual dies before bonding. The overall yield of 3D ICs improves with prebond testability because designers can avoid stacking defective dies with good ones. However, pre-bond testability presents unique challenges to 3D clock tree design. First, each die needs a complete 2D clock tree for the pre-bond testing. In addition, the entire 3D stack needs a complete 3D clock tree for post-bond testing and normal operations. In the case of two-die stack, a straightforward solution is to have two complete 2D clock trees connected with a single Through-Silicon-Via (TSV). We show that this solution suffers from long wirelength and high clock power consumption. Instead, our algorithm minimizes the overall wirelength and clock power consumption while providing the pre-bond testability and post-bond operability under given skew and slew constraints. Compared with the single-TSV solution, SPICE simulation results show that our multi-TSV approa...
Xin Zhao, Dean L. Lewis, Hsien-Hsin S. Lee, Sung K
Added 18 Feb 2011
Updated 18 Feb 2011
Type Journal
Year 2009
Where ICCAD
Authors Xin Zhao, Dean L. Lewis, Hsien-Hsin S. Lee, Sung Kyu Lim
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