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ASPDAC
2015
ACM

Modeling and optimization of low power resonant clock mesh

4 years 7 months ago
Modeling and optimization of low power resonant clock mesh
—Power consumption is becoming more critical in modern integrated circuit (IC) designs and clock network is one of the major contributors for on-chip power. Resonant clock has been investigated as a potential solution to reduce the power consumption in clock network by recycling the energy with on-chip inductors. Most of the previous resonant clock work focuses on H-tree structures, while in this work, we propose a modeling and optimization method for the mesh structure, which suffers from the high power consumption more seriously than the tree structure. Closed-form expressions for the transfer function, skew, and power are derived. Based on these expressions, impacts of design factors, such as the buffer size, LC tank location, grid size, wire width, and the sparsity of buffers and LC tanks, are fully explored to make trade-offs among power, skew, and area, which can be used as design guidelines for top level resonant clock mesh in early design stages. The exploration is also exten...
Wulong Liu, Guoqing Chen, Yu Wang, Huazhong Yang
Added 16 Apr 2016
Updated 16 Apr 2016
Type Journal
Year 2015
Where ASPDAC
Authors Wulong Liu, Guoqing Chen, Yu Wang, Huazhong Yang
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