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Modeling Cache Sharing on Chip Multiprocessor Architectures

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Modeling Cache Sharing on Chip Multiprocessor Architectures
— As CMPs are emerging as the dominant architecture for a wide range of platforms (from embedded systems and game consoles, to PCs, and to servers) the need to manage on-chip resources, such as shared caches, becomes a necessity. In this paper we propose a new statistical model of a CMP shared cache which not only describes cache sharing but also its management via a novel fine-grain mechanism. Our model, called StatShare, accurately describes the behavior of the sharing threads using run-time information (reuse-distance information for memory accesses) and helps us understand how effectively each thread uses its space. The mechanism to manage the cache at the cache-line granularity is inspired by Cache Decay, but contains important differences. Decayed cache-lines are not turned-off to save leakage but are rather “available for replacement.” Decay modifies the underlying replacement policy (random, LRU) to control sharing but in a very flexible and non-strict way which makes it ...
Pavlos Petoumenos, Georgios Keramidas, Håkan
Added 11 Jun 2010
Updated 11 Jun 2010
Type Conference
Year 2006
Where IISWC
Authors Pavlos Petoumenos, Georgios Keramidas, Håkan Zeffer, Stefanos Kaxiras, Erik Hagersten
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