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IBMRD
2006
76views more  IBMRD 2006»
10 years 4 months ago
Modeling wire delay, area, power, and performance in a simulation infrastructure
We present Justice, a set of extensions to the Liberty simulation infrastructure that model area, wire length, and power consumption in processor architectures. Given an architectu...
Nicholas P. Carter, Azmat Hussain
ASPDAC
2008
ACM
126views Hardware» more  ASPDAC 2008»
10 years 6 months ago
DPlace2.0: A stable and efficient analytical placement based on diffusion
Nowadays a placement problem often involves multi-million objects and excessive fixed blockages. We present a new global placement algorithm that scales well to the modern large-s...
Tao Luo, David Z. Pan
ASPDAC
2007
ACM
98views Hardware» more  ASPDAC 2007»
10 years 8 months ago
Fast Analytic Placement using Minimum Cost Flow
Many current integrated circuits designs, such as those released for the ISPD2005[14] placement contest, are extremely large and can contain a great deal of white space. These new...
Ameya R. Agnihotri, Patrick H. Madden
GLVLSI
2000
IEEE
145views VLSI» more  GLVLSI 2000»
10 years 8 months ago
Manhattan or non-Manhattan?: a study of alternative VLSI routing architectures
Circuit interconnect has become a substantial obstacle in the design of high performance systems. In this paper we explore a new routing paradigm that strikes at the root of the i...
Cheng-Kok Koh, Patrick H. Madden
VLSID
2002
IEEE
97views VLSI» more  VLSID 2002»
10 years 9 months ago
Power Supply Noise Aware Floorplanning and Decoupling Capacitance Placement
Power supply noise is a strong function of the switching activities of the circuit modules. Peak power supply noise can be significantly reduced by judiciously arranging the modu...
Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh
DATE
2002
IEEE
102views Hardware» more  DATE 2002»
10 years 9 months ago
Improving Placement under the Constant Delay Model
In this paper, we show that under the constant delay model the placement problem is equivalent to minimizing a weighted sum of wire lengths. The weights can be efficiently compute...
Kolja Sulimma, Wolfgang Kunz, Ingmar Neumann, Luka...
ISVLSI
2007
IEEE
161views VLSI» more  ISVLSI 2007»
10 years 10 months ago
CMP-aware Maze Routing Algorithm for Yield Enhancement
— Chemical-Mechanical Polishing (CMP) is one of the key steps during nanometer VLSI manufacturing process where minimum variation of layout pattern densities is desired. This pap...
Hailong Yao, Yici Cai, Xianlong Hong
DATE
2009
IEEE
129views Hardware» more  DATE 2009»
10 years 11 months ago
Multi-domain clock skew scheduling-aware register placement to optimize clock distribution network
Multi-domain clock skew scheduling is a cost effective technique for performance improvement. However, the required wire length and area overhead due to phase shifters for realizin...
Naser MohammadZadeh, Minoo Mirsaeedi, Ali Jahanian...
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