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A Monitoring-Aware Network-on-Chip Design Flow

12 years 23 days ago
A Monitoring-Aware Network-on-Chip Design Flow
Networks-on-chip (NoC) are a scalable interconnect solution for systems on chip and are rapidly becoming reality. Monitoring is a key enabler for debugging or performance analysis and quality-of-service techniques. The NoC design problem and the NoC monitoring problem cannot be treated in isolation. We propose a monitoring-aware NoC design flow able to take into account the monitoring requirements in general. We illustrate our flow with a debug driven monitoring case study of transaction monitoring. By treating the NoC design and monitoring problems in synergy, the area cost of monitoring can be limited to 3-20% in general.
Calin Ciordas, Andreas Hansson, Kees Goossens, Twa
Added 11 Jun 2010
Updated 11 Jun 2010
Type Conference
Year 2006
Where DSD
Authors Calin Ciordas, Andreas Hansson, Kees Goossens, Twan Basten
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