Sciweavers

ISLPED
2005
ACM
103views Hardware» more  ISLPED 2005»
13 years 10 months ago
A technique for low energy mapping and routing in network-on-chip architectures
Network-on-chip (NoC) has been proposed as a solution for the global communication challenges of System-on-chip (SoC) design in the nanoscale technologies. NoC design with mesh ba...
Krishnan Srinivasan, Karam S. Chatha
DSD
2006
IEEE
72views Hardware» more  DSD 2006»
13 years 11 months ago
A Monitoring-Aware Network-on-Chip Design Flow
Networks-on-chip (NoC) are a scalable interconnect solution for systems on chip and are rapidly becoming reality. Monitoring is a key enabler for debugging or performance analysis...
Calin Ciordas, Andreas Hansson, Kees Goossens, Twa...
DATE
2007
IEEE
173views Hardware» more  DATE 2007»
13 years 11 months ago
Analytical router modeling for networks-on-chip performance analysis
Networks-on-Chip (NoCs) have recently emerged as a scalable alternative to classical bus and point-to-point architectures. To date, performance evaluation of NoC designs is largel...
Ümit Y. Ogras, Radu Marculescu
ISCA
2008
IEEE
188views Hardware» more  ISCA 2008»
13 years 11 months ago
MIRA: A Multi-layered On-Chip Interconnect Router Architecture
Recently, Network-on-Chip (NoC) architectures have gained popularity to address the interconnect delay problem for designing CMP / multi-core / SoC systems in deep sub-micron tech...
Dongkook Park, Soumya Eachempati, Reetuparna Das, ...
DAC
2007
ACM
14 years 6 months ago
The Case for Low-Power Photonic Networks on Chip
Packet-switched networks on chip (NoC) have been advocated as a natural communication mechanism among the processing cores in future chip multiprocessors (CMP). However, electroni...
Assaf Shacham, Keren Bergman, Luca P. Carloni