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DATE
2009
IEEE

MTJ-based nonvolatile logic-in-memory circuit, future prospects and issues

9 years 6 months ago
MTJ-based nonvolatile logic-in-memory circuit, future prospects and issues
—Nonvolatile logic-in-memory architecture, where nonvolatile memory elements are distributed over a logic-circuit plane, is expected to realize both ultra-low-power and reduced interconnection delay. This paper presents novel nonvolatile logic circuits based on logic-in-memory architecture using magnetic tunnel junctions (MTJs) in combination with MOS transistors. Since the MTJ with a spin-injection write capability is only one device that has all the following superior features as large resistance ratio, virtually unlimited endurance, fast read/write accessibility, scalability, complementary MOS (CMOS)-process compatibility, and nonvolatility, it is very suited to implement the MOS/MTJ-hybrid logic circuit with logic-inmemory architecture. A concrete nonvolatile logic-in-memory circuit is designed and fabricated using a 0.18 μm CMOS/MTJ process, and its future prospects and issues are discussed. Keywords-nonvolatile; logic-in-memory; MTJ; standby-powerfree; quick sleep/wake-up
Shoun Matsunaga, Jun Hayakawa, Shoji Ikeda, Katsuy
Added 20 May 2010
Updated 20 May 2010
Type Conference
Year 2009
Where DATE
Authors Shoun Matsunaga, Jun Hayakawa, Shoji Ikeda, Katsuya Miura, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu
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