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DSD
2009
IEEE

Network-on-Chip Architecture Exploration Framework

9 years 8 months ago
Network-on-Chip Architecture Exploration Framework
— In this paper, we present a novel framework for the automated generation of Network-on-Chips (NoC) architectures, that enables architecture exploration and optimization. The automated generation of Network-on-Chip architectures covers beside the generation of the communication infrastructure, the automated integration of IP-components. The automated integration of IP-components is based on IP-XACT interface descriptions of these components. In this paper, we show the integration of components into the Network-on-Chip architecture exemplarily for the SimpleScalar Instruction-Set-Simulator (ISS). The Network-on-Chip architecture used in this paper, is based on a parametrizable switch implemented as Transaction-LevelModel (TLM) in SystemC. The Transaction-Level-Model of the switch provides the possibility of integrating different routing algorithms like deterministic or adaptive routing algorithms. Different Network-on-Chip architectures like mesh-, torus-, and hypercube-topologies ca...
Timo Schönwald, Jochen Zimmermann, Oliver Bri
Added 20 May 2010
Updated 20 May 2010
Type Conference
Year 2009
Where DSD
Authors Timo Schönwald, Jochen Zimmermann, Oliver Bringmann, Wolfgang Rosenstiel
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