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ISPD
2009
ACM

A new algorithm for simultaneous gate sizing and threshold voltage assignment

9 years 6 months ago
A new algorithm for simultaneous gate sizing and threshold voltage assignment
Gate sizing and threshold voltage (Vt) assignment are popular techniques for circuit timing and power optimization. Existing methods, by and large, are either sensitivity-driven heuristics or based on rounding continuous optimization solutions. Sensitivity-driven heuristics are easily trapped in local optimum and the rounding is subject to remarkable errors. In this paper, we propose a systematic combinatorial approach for simultaneous gate sizing and Vt assignment. The core ideas of this approach include consistency relaxation and coupled bi-directional search. Our algorithm is compared with a state-of-the-art previous work on benchmark circuits. The results from our algorithm can lead to about 24% less power dissipation subject to the same timing constraints. Categories and Subject Descriptors B.7 [Integrated Circuits]: Design Aids General Terms Algorithms, Design Keywords Gate Sizing, Threshold Voltage Assignment
Yifang Liu, Jiang Hu
Added 19 May 2010
Updated 19 May 2010
Type Conference
Year 2009
Where ISPD
Authors Yifang Liu, Jiang Hu
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