33 search results - page 1 / 7 » A New Approach to Pipeline FFT Processor |
IPPS
1996
IEEE
13 years 8 months ago
1996
IEEE
A new VLSI architecture for real-time pipeline FFT processor is proposed. A hardware oriented radix-22 algorithm is derived by integrating a twiddle factor decomposition technique ...
ISCAS
2003
IEEE
13 years 9 months ago
2003
IEEE
In this paper, a novel data scaling method for pipelined FFT processors is proposed. By using data scaling, the'FFT processor can operateon a wide range of input signals with...
ICCAD
2003
IEEE
14 years 1 months ago
2003
IEEE
Modeling and simulating pipelined processors in procedural languages such as C/C++ requires lots of cost in handling concurrent events, which hinders fast simulation. A number of ...
ICCAD
1993
IEEE
1993
IEEE
Hardware/software resolution of pipeline hazards in pipeline synthesis of instruction set processors
13 years 8 months ago
— One major problem in pipeline synthesis is the detection and resolution of pipeline hazards. In this paper we present a new solution to the problem in the domain of pipelined a...
SBACPAD
2003
IEEE
13 years 9 months ago
2003
IEEE
Trace reuse improves the performance of processors by skipping the execution of sequences of redundant instructions. However, many reusable traces do not have all of their inputs ...