A Novel Implementation of Tile-Based Address Mapping

Tile-based data layout has been applied to achieve various objectives such as minimizing cache conflicts and memory row switching activity. In some applications of tilebased mapping, the size of the tile can be assumed to be a power of two. In this paper, this `power of two' assumption has been used to drastically simplify the tile-based address mapping functions. Once optimized, the implementation of the non-linear tile-based mapping consumes 60% less power than the implementation of the linear row-major mapping. This result is very interesting because one would normally expect a power penalty in the address generation stage of the more sophisticated tile-based mapping. Moreover, on average tile-based mapping implementation takes 10% less area and incurs virtually no additional delay over row-major mapping implementation.

• Type: Conference
• Year: 2004
• Where: DATE
• Authors: Sambuddhi Hettiaratchi, Peter Y. K. Cheung
• Keywords: DATE 2004, Hardware, Non-linear Tile-based Mapping, Tile-based Mapping, Tile-based Mapping Implementation