PACE: Processor Architectures for Circuit Emulation

We describe a family of reconfigurable parallel architectures for logic emulation. They are supposed to be applicable like conventional FPGAs, while covering a larger range of circuit sizes and clock frequencies. In order to evaluate the performance of such programmable designs, we also need software methods for code generation from circuit descriptions. We propose a combination of scheduling and routing algorithms for embedding calculations into the target architecture.

• Type: Conference
• Year: 1998
• Where: IPPS
• Authors: Reiner Kolla, Oliver Springauf
• Keywords: Circuit Sizes, Conventional Fpgas, Distributed And Parallel Computing, IPPS 1998, Reconfigurable Parallel Architectures