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2003
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Performance and Power Impact of Issue-width in Chip-Multiprocessor Cores

9 years 11 months ago
Performance and Power Impact of Issue-width in Chip-Multiprocessor Cores
In chip-multiprocessors (CMPs), the number of cores and the issue width of each core presents an important design trade-off to balance the amount of TLP and ILP between multi-threaded and single-threaded applications. This paper explores the trade-off between issue-width of the cores and the number of cores on a chip by exploring design points with comparable area with respect to both performance and energy. Despite the fact that several simple cores are advantageous for well-behaved parallel applications, e.g. SPLASH-2, we show that these applications can be run as efficiently and with comparable power consumption on a CMP with fewer, but wider-issue cores. In fact, four-issue cores strike a good balance between ILP and TLP. This is attributable to the inherent ILP and the fact that fewer cores result in less performance and power consumption losses in the on-chip memory hierarchy. Thus, our study shows that opting for moderate issue widths may strike a good compromise between single...
Magnus Ekman, Per Stenström
Added 04 Jul 2010
Updated 04 Jul 2010
Type Conference
Year 2003
Where ICPP
Authors Magnus Ekman, Per Stenström
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