Performance and Power Impact of Issue-width in Chip-Multiprocessor Cores

In chip-multiprocessors (CMPs), the number of cores and the issue width of each core presents an important design trade-off to balance the amount of TLP and ILP between multi-threaded and single-threaded applications. This paper explores the trade-off between issue-width of the cores and the number of cores on a chip by exploring design points with comparable area with respect to both performance and energy. Despite the fact that several simple cores are advantageous for well-behaved parallel applications, e.g. SPLASH-2, we show that these applications can be run as efficiently and with comparable power consumption on a CMP with fewer, but wider-issue cores. In fact, four-issue cores strike a good balance between ILP and TLP. This is attributable to the inherent ILP and the fact that fewer cores result in less performance and power consumption losses in the on-chip memory hierarchy. Thus, our study shows that opting for moderate issue widths may strike a good compromise between single...

• Type: Conference
• Year: 2003
• Where: ICPP
• Authors: Magnus Ekman, Per Stenström
• Keywords: Cores, Distributed And Parallel Computing, ICPP 2003, Issue Widths, Power Consumption