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2010
IEEE

Minimizing the power consumption of a Chip Multiprocessor under an average throughput constraint

9 years 7 months ago
Minimizing the power consumption of a Chip Multiprocessor under an average throughput constraint
- In a multi-core system, power and performance may be dynamically traded off by utilizing power management (PM). This paper addresses the problem of minimizing the total power consumption of a Chip Multiprocessor (CMP) while maintaining a target average throughput. The proposed solution relies on a hierarchical framework, which employs core consolidation, coarse-grain dynamic voltage and frequency scaling (DVFS), and task assignment at the CMP level and fine-grain DVFS based on closed-loop feedback control at the individual core level. Our experimental results are very favorable showing noticeable average power saving compared to a baseline technique, and demonstrate the high efficacy of the proposed hierarchical PM framework. KEYWORDS Chip multiprocessor, Power minimization, Hierarchical power management, Closed-loop control.
Mohammad Ghasemazar, Ehsan Pakbaznia, Massoud Pedr
Added 12 Oct 2010
Updated 12 Oct 2010
Type Conference
Year 2010
Where ISQED
Authors Mohammad Ghasemazar, Ehsan Pakbaznia, Massoud Pedram
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