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DATE
2009
IEEE

Performance-driven dual-rail insertion for chip-level pre-fabricated design

9 years 6 months ago
Performance-driven dual-rail insertion for chip-level pre-fabricated design
In recent years, pre-fabricated design styles grow up rapidly to amortize the mask cost. However, the interconnection delay of the pre-fabricated design styles slows down the circuit performance due to the high capacitive load. In this paper, we propose a technique to insert dual-rail wires for prefabricated design styles. Furthermore, we propose an effective dual-rail insertion algorithm to reduce the routing area overheads caused by the inserted dual-rail wires. Taking the wire criticality, the delay significance, and the wire congestion into consideration, our proposed algorithm is capable of trading additional routing area overheads for the interconnection performance improvement. The experimental results demonstrate that our proposed algorithm reduces the interconnection delay
Fu-Wei Chen, Yi-Yu Liu
Added 20 May 2010
Updated 20 May 2010
Type Conference
Year 2009
Where DATE
Authors Fu-Wei Chen, Yi-Yu Liu
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