Pipelining Saturated Accumulation

8 years 11 months ago
Pipelining Saturated Accumulation
Aggressive pipelining allows FPGAs to achieve high throughput on many Digital Signal Processing applications. However, cyclic data dependencies in the computation can limit pipelining and reduce the efficiency and speed of an FPGA implementation. Saturated accumulation is an important example where such a cycle limits the throughput of signal processing applications. We show how to reformulate saturated addition as an associative operation so that we can use a parallel-prefix calculation to perform saturated accumulation at any data rate supported by the device. This allows us, for example, to design a 16-bit saturated accumulator which can operate at 280MHz on a Xilinx Spartan-3 (XC3S-50004), the maximum frequency supported by the component’s DCM.
Karl Papadantonakis, Nachiket Kapre, Stephanie Cha
Added 24 Jun 2010
Updated 24 Jun 2010
Type Conference
Year 2005
Where FPT
Authors Karl Papadantonakis, Nachiket Kapre, Stephanie Chan, André DeHon
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