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FCCM
2005
IEEE

High-Performance FPGA-Based General Reduction Methods

8 years 12 months ago
High-Performance FPGA-Based General Reduction Methods
FPGA-based floating-point kernels must exploit algorithmic parallelism and use deeply pipelined cores to gain a performance advantage over general-purpose processors. Inability to hide the latency of lengthy pipelines can significantly reduce the performance or impose unrealistic buffer requirements. Designs requiring reduction operations such as accumulation are particularly susceptible. In this paper we introduce two high-performance FPGA-based methods for reducing multiple sets of sequentially delivered floatingpoint values in optimal time without stalling the pipeline.
Gerald R. Morris, Ling Zhuo, Viktor K. Prasanna
Added 24 Jun 2010
Updated 24 Jun 2010
Type Conference
Year 2005
Where FCCM
Authors Gerald R. Morris, Ling Zhuo, Viktor K. Prasanna
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