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DAC
2008
ACM

A power and temperature aware DRAM architecture

9 years 3 months ago
A power and temperature aware DRAM architecture
Technological advances enable modern processors to utilize increasingly larger DRAMs with rising access frequencies. This is leading to high power consumption and operating temperature in DRAM chips. As a result, temperature management has become a real and pressing issue in high performance DRAM systems. Traditional low power techniques are not suitable for high performance DRAM systems with high bandwidth. In this paper, we propose and evaluate a customized DRAM low power technique based on Page Hit Aware Write Buffer (PHA-WB). Our proposed approach reduces DRAM system power consumption and temperature without any performance penalty. Our experiments show that a system with a 64-entry PHA-WB could reduce the total DRAM power consumption by up to 22.0% (9.6% on average). The peak and average temperature reductions are 6.1?C and 2.1?C, respectively. Categories and Subject Descriptors B.3.2 [Memory Structure]: Design Styles ? Primary Memory General Terms Management, Design, Performance...
Song Liu, Seda Ogrenci Memik, Yu Zhang, Gokhan Mem
Added 12 Nov 2009
Updated 12 Nov 2009
Type Conference
Year 2008
Where DAC
Authors Song Liu, Seda Ogrenci Memik, Yu Zhang, Gokhan Memik
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