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2007
IEEE

STEFAL: A System Level Temperature- and Floorplan-Aware Leakage Power Estimator for SoCs

8 years 9 months ago
STEFAL: A System Level Temperature- and Floorplan-Aware Leakage Power Estimator for SoCs
In this paper we demonstrate the impact of the floorplan on the temperature-dependent leakage power of a System on Chip (SoC). We propose a novel system level temperature aware and floorplan aware leakage power estimator, STEFAL, which considers both the floorplan of the SoC and the cycle-by-cycle dynamic power behavior while estimating the leakage power. We implemented our estimation methodology on ten industrial SoC designs from Freescale Semiconductor Inc. and observed up to a 190% difference in the leakage power between various floorplans, clearly showing the importance of considering the floorplans and the temperature profile during leakage power estimation.
Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal
Added 04 Jun 2010
Updated 04 Jun 2010
Type Conference
Year 2007
Where VLSID
Authors Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir
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