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ISCAS
1995
IEEE

Power Dissipation in Deep Submicron CMOS Digital Circuits

10 years 5 months ago
Power Dissipation in Deep Submicron CMOS Digital Circuits
— This paper introduces a simple analytical model for estimating standby and switching power dissipation in deep submicron CMOS digital circuits. The model is based on Berkeley Short-Channel IGFET model and fits HSPICE simulation results well. Static and dynamic power analysis for various threshold voltages is addressed. A design methodology to minimize the power-delay product by selecting the lower and upper bounds of the supply and threshold voltages is presented. The effects of the supply voltage, the threshold voltage, and ; which reflects the drain induced barrier lowing, are also addressed.
R. X. Gu, Mohamed I. Elmasry
Added 26 Aug 2010
Updated 26 Aug 2010
Type Conference
Year 1995
Where ISCAS
Authors R. X. Gu, Mohamed I. Elmasry
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