Sciweavers

ISQED
2005
IEEE

Deep Submicron CMOS Integrated Circuit Reliability Simulation with SPICE

13 years 9 months ago
Deep Submicron CMOS Integrated Circuit Reliability Simulation with SPICE
The purpose of the paper is to introduce a new failure rate-based methodology for reliability simulation of deep submicron CMOS integrated circuits. Firstly, two of the state-of-the-art MOSFET degradation models are reviewed. They have been developed into reliability simulation tools and commercialized in industry for many years, however, their inherent limitations of characterizing circuit lifetime, including tedious processes for extracting device degradation parameters and model fitting parameters, impeded their wide applications in the product’s front-end design process. Secondly, a set of accelerated lifetime models for the most important intrinsic silicon degradation mechanisms are proposed. These lifetime models correlate a device’s electrical operating parameters to its mean time to failure (MTTF) in simple forms. Finally, a new failure ratebased SPICE reliability simulation methodology is developed, in which MTTF and failure in time (FIT) are the primary reliability para...
Xiaojun Li, Bing Huang, J. Qin, X. Zhang, Michael
Added 25 Jun 2010
Updated 25 Jun 2010
Type Conference
Year 2005
Where ISQED
Authors Xiaojun Li, Bing Huang, J. Qin, X. Zhang, Michael Talmor, Z. Gur, Joseph B. Bernstein
Comments (0)