A Power-Efficient Floating-Point Co-processor Design

11 years 3 months ago
A Power-Efficient Floating-Point Co-processor Design
According to dramatically growing interesting in power-efficient embedded processor, designers must establish the proper power strategy when they design new embedded processor cores. This paper develops a SPARC compatible floating-point co-processor, which is part of a SPARC compatible embedded processor, which implements the SPARC V8 floatingpoint instruction set except for square root and all quad precision instructions. To lower the power dissipation of floating-point coprocessor, we modify the decoder stage of the integer unit pipeline to generate the clock gating signals so that the unused floatingpoint co-processor execution pipeline can be clock-gated. The design is implemented in a SMIC 0.18-
Xunying Zhang, Xubang Shen
Added 19 Oct 2010
Updated 19 Oct 2010
Type Conference
Year 2008
Where CSSE
Authors Xunying Zhang, Xubang Shen
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