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2007
ACM

Power optimal MTCMOS repeater insertion for global buses

9 years 9 months ago
Power optimal MTCMOS repeater insertion for global buses
This paper addresses the problem of power-optimal repeater insertion for global buses in the presence of crosstalk noise. MTCMOS technique by inserting high-Vth sleep transistors to reduce the leakage power consumption in the idle mode is used. We simultaneously calculate the repeater sizes, repeater distances, and the size of the sleep transistors to minimize the power dissipation. The effect of crosstalk coupling capacitance on propagation delay and (switching and short circuit) power dissipation is considered. Experimental results show that depending on the activity factor of the circuit, the proposed technique can significantly reduce the power consumption of the global bus interconnects. Categories and Subject Descriptors B.8.2 [Performance and Reliability]: Performance Analysis and Design Aides General Terms Algorithms, Design, Performance Keywords Low-power design, buffer insertion, MTCMOS circuits
Hanif Fatemi, Behnam Amelifard, Massoud Pedram
Added 26 Oct 2010
Updated 26 Oct 2010
Type Conference
Year 2007
Where ISLPED
Authors Hanif Fatemi, Behnam Amelifard, Massoud Pedram
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