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ISCA
2012
IEEE
333views Hardware» more  ISCA 2012»
8 years 3 days ago
Reducing memory reference energy with opportunistic virtual caching
Most modern cores perform a highly-associative translation look aside buffer (TLB) lookup on every memory access. These designs often hide the TLB lookup latency by overlapping it...
Arkaprava Basu, Mark D. Hill, Michael M. Swift
ECCTD
2011
72views more  ECCTD 2011»
8 years 9 months ago
Managing variability for ultimate energy efficiency
⎯ Technology scaling is in the era where the chip performance is constrained by its power dissipation. Although the power limits vary with the application domain, they dictate th...
Borivoje Nikolic
TVLSI
2010
9 years 4 months ago
Area and Power Optimization of High-Order Gain Calibration in Digitally-Enhanced Pipelined ADCs
Digital calibration techniques are widely utilized to linearize pipelined analog-to-digital converters (ADCs). However, their power dissipation can be prohibitively high, particula...
Mohammad Taherzadeh-Sani, Anas A. Hamoui
ANCS
2009
ACM
9 years 7 months ago
Design of a scalable nanophotonic interconnect for future multicores
As communication-centric computing paradigm gathers momentum due to increased wire delays and excess power dissipation with technology scaling, researchers have focused their atte...
Avinash Karanth Kodi, Randy Morris
ISQED
2010
IEEE
176views Hardware» more  ISQED 2010»
9 years 8 months ago
A 2-port 6T SRAM bitcell design with multi-port capabilities at reduced area overhead
Low power, minimum transistor count and fast access static random access memory (SRAM) is essential for embedded multimedia and communication applications realized using system on...
Jawar Singh, Dilip S. Aswar, Saraju P. Mohanty, Dh...
ISQED
2010
IEEE
133views Hardware» more  ISQED 2010»
9 years 8 months ago
UC-PHOTON: A novel hybrid photonic network-on-chip for multiple use-case applications
Multiple use-case chip multiprocessor (CMP) applications require adaptive on-chip communication fabrics to cope with changing use-case performance needs. Networks-on-chip (NoC) ha...
Shirish Bahirat, Sudeep Pasricha
TVLSI
2002
104views more  TVLSI 2002»
9 years 9 months ago
A comparative analysis of low-power low-voltage dual-edge-triggered flip-flops
This paper compares four previously published static dual-edge-triggered flip-flops (DETFFs) with a proposed design for their performance, power dissipation, and low-voltage low-po...
Wai Chung, Timothy Lo, Manoj Sachdev
FTEDA
2008
75views more  FTEDA 2008»
9 years 9 months ago
Thermally Aware Design
With greater integration, the power dissipation in integrated circuits has begun to outpace the ability of today's heat sinks to limit the on-chip temperature. As a result, t...
Yong Zhan, Sanjay V. Kumar, Sachin S. Sapatnekar
USENIX
2003
9 years 11 months ago
Design and Implementation of Power-Aware Virtual Memory
Despite constant improvements in fabrication technology, hardware components are consuming more power than ever. With the everincreasing demand for higher performance in highly-in...
Hai Huang, Padmanabhan Pillai, Kang G. Shin
ISLPED
2007
ACM
138views Hardware» more  ISLPED 2007»
9 years 11 months ago
Power optimal MTCMOS repeater insertion for global buses
This paper addresses the problem of power-optimal repeater insertion for global buses in the presence of crosstalk noise. MTCMOS technique by inserting high-Vth sleep transistors ...
Hanif Fatemi, Behnam Amelifard, Massoud Pedram
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