Optimization of combinational and sequential logic circuits for low power using precomputation

Precomputation is a recently proposed logic optimization technique which selectively disables the inputs of a sequential logic circuit, thereby reducing switching activity and power dissipation, without changing logic functionality. In this paper, we presentnew precomputation architecturesfor both combinational and sequential logic and describe new precomputation-based logic synthesis methods that optimize logic circuits for low power. We present a general precomputation architecture for sequential logic circuits and show that it is significantly more powerful than the architectures previously treated in the literature. In this architecture, output values required in a particular clock cycle are selectively precomputed one clock cycle earlier, and the original logic circuit is “turned off” in the succeeding clock cycle. The very power of this architecture makes the synthesis of precomputation logic a challenging problem and we present a method to automatically synthesize precompu...

• Type: Conference
• Year: 1995
• Where: ARVLSI
• Authors: José Monteiro, John Rinderknecht, Srinivas Devadas, Abhijit Ghosh
• Keywords: ARVLSI 1995, Logic, Logic Circuit, Sequential Logic, VLSI