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2005
IEEE

Rapid Embedded Hardware/Software System Generation

9 years 9 months ago
Rapid Embedded Hardware/Software System Generation
This paper presents an RTL generation scheme for a SimpleScalar / PISA Instruction set architecture with system calls to implement C programs. The scheme utilizes ASIPmeister, a processor generation tool. The RTL generated is available for download. The second part of the paper shows a method of reducing the PISA instruction set and generating a processor for a given application. This reduction and generation can be performed within an hour, making this one of the fastest methods of generating an application specific processor. For five benchmark applications, we show that on average, processor size can be reduced by 30% , energy consumed reduced by 24%, and performance improved by 24%.
Jorgen Peddersen, Seng Lin Shee, Andhi Janapsatya,
Added 01 Dec 2009
Updated 01 Dec 2009
Type Conference
Year 2005
Where VLSID
Authors Jorgen Peddersen, Seng Lin Shee, Andhi Janapsatya, Sri Parameswaran
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