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ICASSP
2011
IEEE

Reconfigurable decoder architectures for Raptor codes

8 years 7 months ago
Reconfigurable decoder architectures for Raptor codes
Decoder architectures for architecture-aware Raptor codes having regular message access-and-processing patterns are presented. Raptor codes are a class of concatenated codes composed of a fixedrate precode and a Luby-Transform (LT) code that can be used as rate-less error-correcting codes over communication channels. In the proposed approach, the decoding procedure is mapped to row processing of a regular matrix, which adapts effectively to the code’s randomness and degree-irregularity. This is achieved by 1) developing reconfigurable check node processors that attain a constant throughput while processing LT- and LDPC-nodes of varying degrees and numbers, 2) applying pseudo-random permutation on the communicated messages, and 3) computing bit-tocheck messages in a serial, temporally distributed manner. A serial decoder for a rate-0.4 code implementing the proposed approach was synthesized in 65nm CMOS technology. Hardware simulations show that the decoder achieves a throughput of...
Hady Zeineddine, Mohammad M. Mansour
Added 20 Aug 2011
Updated 20 Aug 2011
Type Journal
Year 2011
Where ICASSP
Authors Hady Zeineddine, Mohammad M. Mansour
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