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DAC
2006
ACM

A reconfigurable design-for-debug infrastructure for SoCs

9 years 5 months ago
A reconfigurable design-for-debug infrastructure for SoCs
In this paper we present a Design-for-Debug (DFD) reconfigurable infrastructure for SoCs to support at-speed in-system functional debug. A distributed reconfigurable fabric inserted at RTL provides a debug platform that can be configured and operated post-silicon via the JTAG port. The platform can be repeatedly reused to configure many debug structures such as assertions checkers, transaction identifiers, triggers, and event counters. Categories and Subject Descriptors B.7 [Integrated circuits]; J.6 [Computer-aided engineering] General Terms Verification, Performance, Design, Economics, Experimentation.
Miron Abramovici, Paul Bradley, Kumar N. Dwarakana
Added 13 Jun 2010
Updated 13 Jun 2010
Type Conference
Year 2006
Where DAC
Authors Miron Abramovici, Paul Bradley, Kumar N. Dwarakanath, Peter Levin, Gérard Memmi, Dave Miller
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