Reencoding for cycle-time minimization under fixed encoding length

This paper presents efficient reencoding and resynthesis algorithms for cycle-time minimization of multilevel implementations of synchronous finite state machines (FSMs) under a fixed encoding length. The proposed technique is applicable to both gate-level and technology independent synchronous network representations. We present two algorithms for identifying useful reencodings

• Type: Conference
• Year: 1998
• Where: ICCAD
• Authors: Balakrishnan Iyer, Maciej J. Ciesielski
• Keywords: Hardware, ICCAD 1998, Independent Synchronous Networks, Synchronous Finite State, Synchronous Network Representations