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HPCA
1996
IEEE

Register File Design Considerations in Dynamically Scheduled Processors

12 years 3 months ago
Register File Design Considerations in Dynamically Scheduled Processors
We have investigated the register file requirements of dynamically scheduled processors using register renaming and dispatch queues running the SPEC92 benchmarks. We looked at processors capable of issuing either four or eight instructions per cycle and found that in most cases implementing precise exceptions requires a relatively small number of additional registers compared to imprecise exceptions. Systems with aggressive non-blocking load support were able to achieve performance similar to processors with perfect memory systems at the cost of some additional registers. Given our machine assumptions, we found that the performance of a four-issue machine with a 32-entry dispatch queue tends to saturate around 80 registers. For an eight-issue machine with a 64-entry dispatch queue performance does not saturate until about 128 registers. Assuming the machine cycle time is proportional to the register file cycle time, the 8-issue machine yields only 20% higher performance than the 4-iss...
Keith I. Farkas, Norman P. Jouppi, Paul Chow
Added 07 Aug 2010
Updated 07 Aug 2010
Type Conference
Year 1996
Where HPCA
Authors Keith I. Farkas, Norman P. Jouppi, Paul Chow
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