Register renaming and dynamic speculation: an alternative approach

In this paper, we present a novel mechanism that implements register renaming, dynamic speculation and precise interrupts. Renaming of registers is performed during the instruction fetch stage instead of the decode stage, and the mechanism is designed to operate in parallel with the tag match logic used by most cache designs. It is estimated that the critical path of the mechanism requires approximately the same number of logic levels as the tag match logic, and therefore should not impact cycle time.

• Type: Conference
• Year: 1993
• Where: MICRO
• Authors: Mayan Moudgill, Keshav Pingali, Stamatis Vassiliadis
• Keywords: Hardware, Instruction Fetch Stage, MICRO 1993, Register Renaming, Tag Match Logic