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2011
IEEE

Reliability-Aware Design Optimization for Multiprocessor Embedded Systems

7 years 6 months ago
Reliability-Aware Design Optimization for Multiprocessor Embedded Systems
—This paper presents an approach for the reliability-aware design optimization of real-time systems on multi-processor platforms. The optimization is based on an extension of well accepted fault- and process-models. We combine utilization of hardware replication and software reexecution techniques to tolerate transient faults. A System Fault Tree (SFT) analysis is proposed, which computes the systemlevel reliability in presence of the hardware and software redundancy based on component failure probabilities. We integrate the SFT analysis with a Multi-Objective Evolutionary Algorithm (MOEA) based optimization process to perform efficient reliability-aware design space exploration. The solution resulting from our optimization contains the mapping of tasks to processing elements (PEs), the exact task and message schedule and the fault-tolerance policy assignment. The effectiveness of the approach is illustrated using several case studies.
Jia Huang, Jan Olaf Blech, Andreas Raabe, Christia
Added 19 Dec 2011
Updated 19 Dec 2011
Type Journal
Year 2011
Where DSD
Authors Jia Huang, Jan Olaf Blech, Andreas Raabe, Christian Buckl, Alois Knoll
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