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2005
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Reliability-Conscious Process Scheduling under Performance Constraints in FPGA-Based Embedded Systems

9 years 7 months ago
Reliability-Conscious Process Scheduling under Performance Constraints in FPGA-Based Embedded Systems
This paper proposes, for the FPGA-based embedded systems, a reliability-aware process scheduling strategy that operates under performance bounds. A unique characteristic of the proposed approach is that it employs multiple implementations (also called versions) of a given process; each version differs from the other implementations (of the same process) from the viewpoint of reliability, performance, power, or area metrics. Our scheme, which can work under a base scheduler or independently, tries to use the most reliable version for each process, restricted only by the performance bound specified. We implemented this scheme and simulated it using a custom simulator.
Guilin Chen, Mahmut T. Kandemir, Suleyman Tosun, U
Added 25 Jun 2010
Updated 25 Jun 2010
Type Conference
Year 2005
Where IPPS
Authors Guilin Chen, Mahmut T. Kandemir, Suleyman Tosun, Ugur Sezer
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